MAX4617/MAX4618/MAX4619/Multiplexers&SN74HC139Demultiplexer技术参考文档

MAX4617/MAX4618/MAX4619/Multiplexers说明The MAX4617/MAX4618/MAX4619 are high-speed, low-voltage, CMOS analog ICs configured as an 8-channel multiplexer (MAX4617), two 4-channel multiplexers (MAX4618), and three single-pole/double-throw (SPDT) switches (MAX4619).

These CMOS devices can operate continuously with a +2V to +5.5V single supply. Each switch can handle rail-to-rail analog signals. The off-leakage current is only 1nA at TA = +25°C and 10nA at TA = +85°C.

All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS-logic compatibility when using a single +5V supply.

MAX4617、MAX4618、MAX4619：引脚配置


关键特性

• Fast Switching Times
  
  • 15ns tON
  • 10ns tOFF
    
• Pin Compatible with Industry-Standard 74HC4051/74HC4052/74HC4053 and MAX4581/MAX4582/MAX4583
• Guaranteed On-Resistance
  
  • 10Ω max (+5V Supply)
  • 20Ω max (+3V Supply)
    
• Guaranteed 1Ω On-Resistance Match Between Channels (single +5V supply)
• Guaranteed Low Off-Leakage Current: 1nA at +25°C
• Guaranteed Low On-Leakage Current: 1nA at +25°C
• +2V to +5.5V Single-Supply Operation
• TTL/CMOS-Logic Compatible
• Low Crosstalk: < -96dB
• High Off-Isolation: < -93dB
• Low Distortion: < 0.017% (600Ω)
  

技术参考文档：


SN74HC139
双路 2 线路至 4 线路解码器/多路解复用器
描述

The ’HC139 devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The ’HC139 devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G\) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

特性

• Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
• Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80-µA Max ICC
• Typical tpd = 10 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 µA Max
• Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  

技术参考文档：